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CVE-2023-34326
Date: January 5, 2024
The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
Language: C
Severity Score
Severity Score
Weakness Type (CWE)
Insufficient Information
NVD-CWE-noinfoCVSS v3
| Base Score: |
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|---|---|
| Attack Vector (AV): | |
| Attack Complexity (AC): | |
| Privileges Required (PR): | |
| User Interaction (UI): | |
| Scope (S): | |
| Confidentiality (C): | NONE |
| Integrity (I): | PARTIAL |
| Availability (A): | NONE |