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CVE-2025-45006

Date: June 30, 2025

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

Severity Score

Related Resources (5)

https://github.com/chipsalliance/rocket-chip.git
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications
https://nvd.nist.gov/vuln/detail/CVE-2025-45006
https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md
https://www.mend.io/vulnerability-database/CVE-2025-45006

Severity Score

Weakness Type (CWE)

Incorrect Privilege Assignment

CWE-266

CVSS v3.1

Base Score:
Attack Vector (AV): NETWORK
Attack Complexity (AC): LOW
Privileges Required (PR): NONE
User Interaction (UI): NONE
Scope (S): UNCHANGED
Confidentiality (C): HIGH
Integrity (I): NONE
Availability (A): HIGH

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